The following U.S. patents are believed to represent the current state of the art: U.S. Pat. Nos. 5,963,495, 6,703,907, 6,529,085, 6,815,980, 6,388,495, and 6,556,628 . These patents all relate to prior art with respect to the current patent.
When semiconductor's smallest dimensions were much larger than a micron, line spaces and widths for the metal interconnect between the transistors were much larger than their thickness. Also there were only a few layers of metal. As a result signals propagated down wires in a fashion similar to a resistive transmission line. The primary components of delay at that time were the capacitance to the ground plane and the resistance of the wire.
FIG. 1 shows a side view of such wires 10 and vias 11 between two layers 12 of metal.
Typically, when multiple layers of metal were used, they were organized in parallel tracks on each layer, and perpendicular to each other. FIG. 2 shows such a structure with vertical wire segments 20 on one layer, and horizontal segments 21, on a different layer, interconnected with vias 22.
As the dimensions shrank and the number of metal interconnect layers grew, the capacitance due to the adjacent wires became more significant, and efforts began to reduce the dielectric constant of the insulating glass.
Reference is now made to FIG. 3, a cross section of two layers 32, of interconnect wire in a deep sub-micron process. Now that current dimensions are below 0.1 microns, the effort to minimize the resistance has resulted in constructing wires 30, which are much thicker than they are wide, with spaces that are much closer than the distances between the layers. As a result the sidewall capacitance is much more significant than the ground plane capacitance.
As semiconductor dimensions have continued to shrink, the device delays continue to shrink as well, but the inevitable increases in capacitance and resistance due to these smaller dimensions have now kept the wire interconnect delay relatively constant, even though the average wire length continues to shrink with the chips.
It has gotten to the point at 100 nanometer (0.1 micron) dimensions, where the wire delay is greater than the device delay, and long wire signal propagation delay is now over 10 clock cycles on high performance chips.
Furthermore, the side wall capacitance couples the signals between adjacent wires, and while most wire segments 40 as shown in FIG. 4, are short, there are an increasing number of long segments 41 that are adjacent to each other over a long enough length to cause significant enough capacitive coupling, to functionally fail in normal operation.
Traditionally, transmitters on long lines are designed with high drive to charge up the line as quickly as possible and receivers are designed with thresholds in the mid range of their voltage swings for maximum noise immunity, which means the line must be charged past mid voltage before the receiver switches. The added capacitance and resistance of the wires in sub 100 nanometer processes has slowed this charging and discharging even as the transmitter's drive increases due to the shorter gate lengths, resulting in longer delays for these long lines.
A different approach is needed to constructing long metal interconnects on deep sub-micron Integrated Circuits (ICs). Such a structure must be more immune to adjacent wire cross talk, propagate signals at much higher velocity than current interconnects, while sustaining the fast transition times the current devices are capable of, and receivers must be used that sense the significantly attenuated signals that arrive at the other end of the long metal lines.
Typically long metal interconnects on ICs have high resistive and capacitive losses, which severely degrades their transition times and propagation delays, as well as making them subject to adjacent signal inductive and capacitive coupling. Instead, using tightly coupled transmission lines has the advantage of limiting the impedance to the differential characteristics of the line, predominantly the coupling capacitance between the two lines. Furthermore, because the differential signals cancel, the EMI losses are minimized, reducing the aggressor and victim cross talk characteristics in adjacent lines. Also inductive coupling tends to preserve rather than impede the transitions on the lines. The propagation time is improved, since differential transmission signal velocity is higher than common transmission signal velocity.
Lastly, when current is sensed by differential receivers, rather than voltage on single ended receivers, the receivers can be designed to switch on the first incident of the signals, as opposed to waiting until the voltage passes the threshold of the device, which will only occur after the long line is sufficiently charged up.
Prior art covers the concepts of transmission lines and differential current receivers, but not the concept of applying these to on-chip communications. Tran in U.S. Pat. No. 4,991,141, granted Feb. 5, 1991, and Kumar in U.S. Pat. No. 5,963,495, granted Oct. 5, 1999, talk about differential receivers for use in memories. Others such as van der Wagt in U.S. Pat. No. 6,703,907, granted Mar. 9,2004, and Hajimiri et al. in U.S. Pat. No. 6,529,085, granted Mar. 4, 2003, talk about using differential transmission lines for various analog devices, while Kerr in U.S. Pat. No. 6,815,980, granted Nov. 9, 2004, and Roy, et al. in U.S. Pat. No. 6,388,495, granted May 14, 2002, discuss the need for differential transmission line drivers and receivers for chip to chip communication. Also, Poulton, et al. in U.S. Pat. No. 6,556,628, granted Apr. 29, 1999, describe the need for getting more bandwidth out of off chip differential transmission lines because of the chip to chip bandwidth issue. They do not talk about using differential transmission lines for internal chip communication, because up to now there has not been an on-chip bandwidth issue. In fact, M. Mizuno and W. J. Dally present a case in, “Elastic Interconnects: Repeater-Inserted Long Wiring Capable of Compressing and Decompressing Data,” 2001 ISSCC, Feb. 2001, pp. 346-347, for improving on-chip long wire performance by inserting a large number of repeaters into the wires, which takes more transistors and wire. Clearly the problem is not bandwidth, but performance.
As the dimensions shrink and the number of interconnect layers grows, there is plenty of space for on-chip interconnect, but without improvements such as described in this disclosure, the performance of Integrated Circuits will not be improved by going to smaller process dimensions.
The solution is to use differential current sensing receivers coupled with differential transmitters for global interconnect as described in “Current Sensing Techniques for Global Interconnects in Very Deep Submicron (VDSM) CMOS”, by Atul Maheshwari and Wayne Burleson, of Dept. of Electrical & Computer Engineering, University of Massachusetts, Amherst MA. Burleson further defines an improved current sensing device in “Current-Sensing for Crossbars*”, by Manoj Sinha and Wayne Burleson, of Dept. of Electrical & Computer Engineering, University of Massachusetts, Amherst Mass. This patent expands on this initial work.